1. Field of the Invention
The present invention relates to an encode circuit used for a high-speed A/D (Analog-Digital) converter. More particularly, the present invention provides an encoding method, efficient for the cyclic thermometer codes used for a high-speed folding-type A/D converter that uses an A/D conversion method whose resolution can be increased easier than that of a flash type A/D converter, and an encode circuit that uses cyclic thermometer codes.
The present application contains subject matter related to Japanese Patent Application JP 2006-132550 filed in the Japanese Patent Office on May 11, 2006, the entire content of which being incorporated herein by reference.
2. Description of Related Art
FIG. 15 shows the configuration of a flash-type A/D (Analog to Digital) converter, which outputs 3-bit binary code, as an example of a high-speed A/D converter of related art. As shown in FIG. 15, a standard flash-type A/D converter 700 includes comparator units, 710-716, that compare an analog input signal Ain with a reference voltage generated by a ladder of resistors 701-708 to generate thermometer codes corresponding to the magnitude of the input signal, logical boundary detection unit, 720-727, that detects the logical boundary point between 1 and 0 in the thermometer codes, and an encoder unit, 731-733 and 741-751, that outputs binary code B[2:0] based on the output signal from the logical boundary detection unit.
In the comparator unit composed of comparators 710-716, the voltage between the high-voltage side reference voltage Vrt and the low-voltage side reference voltage Vrb is divided by the ladder of eight resistors 701-708 into seven reference voltages Vr0-Vr6. The resistance value of the resistors 701 and 708 at both ends is set to the half of the value of other resistors. The analog input signal Ain is compared with the seven divided reference voltages by the seven comparators CMP0-CMP6 (710-716).
When the analog input signal Ain is higher than the reference voltage Vr0-Vr6, the output signal CP0-CP6 of the comparators CMP0-CMP6 (710-716) is set to 1 and the output signal CN0-CN6 is set to 0. Conversely, when Ain is lower than the reference voltage Vr0-Vr6, the output signal CN0-CN6 is set to 1 and the output signal CP0-CP6 is set to 0. Therefore, when Ain is higher than the reference voltage Vr3 but lower than Vr4, the thermometer codes are generated as follows: CP0-CP3 are set to 1, CP4-CP6 are set to 0, CN0-CN3 are set to 0, and CN4-CN6 are set to 1.
In the logical boundary detection unit, the thermometer code outputs CP0-CP6 and CN0-CN6 from the comparator unit CMP0-CMP6 (710-716) are supplied to three-input NOR circuits NR0-NR7 (720-727), as shown in FIG. 15. The output signals CNi−1, CPi, and CPi+1 of a comparator are input to NRi (i is an integer). That is, only when (CPi−1, CPi, CPi+1)=(1, 0, 0), the output of NRi is 1 and the point at which a sequence of 1 is changed to a sequence of 0 is output as the logical boundary point.
The encoder unit includes PMOS transistors MP1-MP3 (731-733), which pre-charge bit lines BL0-BL2 to the power supply voltage VDD by setting the Encode signal to the L level, and NMOS transistors MN1-MN12 (741-751) which pull down the corresponding bit of the pre-charged bit lines BL0-BL2 to GND (ground), based on output word lines WL0-WL7 from the logical boundary detection unit, to give desired binary outputs B0-B2.
Therefore, when the input signal Ain, which is higher than the reference voltage Vr3 but lower than Vr4, is received after the Encode signal is set to “L” level to pre-charge the bit lines BL0-BL2 to the power supply voltage VDD, only word line WL4 is set to the H level by the logical boundary detection unit and the NMOS transistors MN3 (748) and MN4 (749) are turned on. At this time, when the Encode signal is set to the H level, bit lines BL1 and BL0 are pulled down to GND and the encoded binary signal B[2:0]=100 is output. Note that B[2:0] indicates three-bit data ranging from 2 to 0.
In an A/D converter that uses such thermometer codes, there is a bubble error in the thermometer codes which needs to be handled with care. For example, in the comparator outputs CP0-CP, as shown in FIG. 15, there should be only one point where the value changes between 1 and 0 such as 1111100. A bubble error refers to two or more points of change between 1 and 0 in the comparator outputs, such as 1011100. This bubble error turns on two or more word lines at the same time and so generates a large error in the output code.
However, when the standard thermometer codes are used, the output of a three-input NOR circuit is 1 only when three continuous values of the thermometer codes is (1, 0, 0) as in the configuration of the logical boundary detector shown in FIG. 15. For example, even if the comparator outputs from CMP0-CMP6 (710-716) in FIG. 15 become 1011100 due to a bubble error, only NR5 (725) out of NR0-NR7 (720-727) outputs 1 and, therefore, the same binary code is output as when the comparator output of CMP0-CMP6 (710-716) is 1111100.
In contrast to the A/D converter described above, a folding-type A/D converter, known as another high-speed A/D converter comparable to the flash-type A/D converter, and cyclic thermometer codes are disclosed by ROB E. J, VAN DE GRIFT et al. in “An 8-bit video ADC incorporating folding and interpolation techniques” (IEEE Journal of Solid-State Circuits, Volume 22, Issue 6, December 1987, pp. 944 953).
As shown in FIG. 16, these cyclic thermometer codes are codes generated by a repetitive operation in which the codes are sequentially filled with 1 beginning with the lower-order side of the cyclic thermometer codes from the comparators and, when the codes are all filled with 1, the codes are sequentially filled with 0 beginning with the lower-order side and, when the codes are all filled with 0, the codes are sequentially filled with 1 again beginning with the lower-order side. Because there is only one point of change from 1 to 0 or from 0 to 1 between each two neighboring values, this code system is especially suited for an A/D converter used in high-speed operation.